DocID024597 Rev 3 735/1693
RM0351 Advanced encryption standard hardware accelerator (AES)
751
Note: 1 For mode 2 (key derivation), access to the AES_KEYRx registers can be done by software
using the CPU. No DMA channel is provided for this purpose. Consequently, the DMAINEN
bit and DMAOUTEN bits in the AES_CR register have no effect during this mode.
2 The CCF flag is not relevant when DMAOUTEN = 1 and software does not need to read it in
this case. This bit may stay high and has to be cleared by software if the application needs
to disable the AES to cancel the DMA management and use CPU access for the data input
or data output phase.
Figure 186. DMA requests and data transfers during Input phase (AES_IN)
Figure 187. DMA requests during Output phase (AES_OUT)
25.11 Error flags
The AES read error flag (RDERR) in the AES_SR register is set when an unexpected read
operation is detected during the computation phase or during the input phase.
The AES write error flag (WRERR) in the AES_SR register is set when an unexpected write
operation is detected during the output phase or during the computation phase.
The flags may be cleared setting the respective bit in the AES_CR register (CCFC bit to
clear the CCF flag, ERRC bit to clear the WERR and RDERR flags).
An interrupt can be generated when one of the error flags (WERR or RDERR) is set if the
error interrupt enable (ERRIE) bit in the AES_CR register has been previously set.
If an error is detected, AES is not disabled by hardware and continues processing as
normal.
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