USB on-the-go full-speed (OTG_FS) RM0351
1548/1693 DocID024597 Rev 3
43.15.15 OTG power down register (OTG_GPWRDN)
Address offset: 0x058
Reset value: 0x0000 0010
43.15.16 OTG ADP timer, control and status register
(OTG_GADPCTL)
Address offset: 0x060
Reset value: 0x0000 0000
The OTG_GADPCTL register must be accessed as follows:
• In order to read from the OTG_GADPCTL register, program AR=0b01 and keep polling
till AR=0b00. The core updates the other fields of this register and makes AR=0b00.
Read values of this register are valid only when AR=0b00.
• In order to write to the OTG_GADPCTL register, program AR=0b10 along with the
values for the other fields and keep polling till AR=0b00. When AR becomes 0b00, it
means that the programmed value has taken effect inside the core.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. ADPIF Res. Res. Res. Res. Res. Res. Res.
rc_w1
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
ADPM
EN
rw
Bits 31:24 Reserved, must be kept at reset value.
Bit 23 ADPIF: ADP interrupt flag
This bit is set whenever there is an ADP event
Bits 22:1 Reserved, must be kept at reset value.
Bit 0 ADPMEN: ADP module enable
This bit enables or disables the ADP logic.
0: Disable ADP module
1: Enable ADP module
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. AR
ADP
TOIM
ADP
SNSIM
ADP
PRBIM
ADP
TOIF
ADP
SNSIF
ADP
PRBIF
ADPEN
ADP
RST
ENA
SNS
ENA
PRB
RTIM
rw rw rw rw rw rc_w1 rc_w1 rc_w1 rw rs rw rw r
1514131211109876543210
RTIM PRBPER PRBDELTA PRBDSCHG
rrrrrrrrrrrwrwrwrwrwrw
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