DocID024597 Rev 3 1549/1693
RM0351 USB on-the-go full-speed (OTG_FS)
1644
Bits 31:29 Reserved, must be kept at reset value.
Bits 28:27 AR: Access request
This bitfield define the requested access mode to the
OTG_GADPCTL register:
00 Read / Write valid (updated by the core)
01 Read request
10 Write request
11 Reserved
Bit 26 ADPTOIM: ADP timeout interrupt mask
When this bit is set, it unmasks the interrupt from ADPTOIF.
Bit 25 ADPSNSIM: ADP sense interrupt mask
When this bit is set, it unmasks the interrupt from ADPSNSIF.
Bit 24 ADPPRBIM: ADP probe interrupt mask
When this bit is set, it unmasks the interrupt from ADPPRBIF.
Bit 23 ADPTOIF: ADP timeout interrupt flag
This bit is relevant only for an ADP probe. When this bit is set, it means that the ramp
time has completed (RTIM has reached its terminal value of 0x7FF). This is a debug
feature that allows the application to read the ramp time after each cycle.
Bit 22: ADPSNSIF: ADP sense interrupt flag
When this bit is set, it means that the V
BUS
voltage is greater than V
ADPSNS
value or that
V
ADPSNS
is reached.
Bit 21 ADPPRBIF: ADP probe interrupt flag
When this bit is set, it means that the V
BUS
voltage is greater than V
ADPPRB
or that
V
ADPPRB
is reached.
Bit 20 ADPEN: ADP enable
When set, the core performs either ADP probing or sensing based on ENAPRB or
ENASNS.
Bit 19 ADPRST: ADP reset
When set, ADP controller is reset. This bit is auto-cleared after the reset procedure is
complete in the ADP controller.
Bit 18 ENASNS: Enable sense
When programmed to 1, the core performs a sense operation.
Bit 17 ENAPRB: Enable probe
When programmed to 1, the core performs a probe operation.
Bits 16:6 RTIM: Ramp time
These bits capture the latest time it took for V
BUS
to ramp from V
ADPSINK
to V
ADPPRB
. The
bits are defined in units of 32 kHz clock cycles as follow:
000: 1 cycle
001: 2 cycles
002: 3 cycles
...
7FF: 2048 cycles
A time of 1024 cycles at 32 kHz corresponds to a time of 32 ms.
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