Digital filter for sigma delta modulators (DFSDM) RM0351
616/1693 DocID024597 Rev 3
21.3.5 Configuring the input serial interface
The following parameters must be configured for the input serial interface:
• Output clock predivider. There is a programmable predivider to generate the output
clock from DFSDM clock (2 - 256). It is defined in DFSDMx_CR1 register.
• Serial interface type and input clock phase. Selection of SPI or Manchester coding
and sampling edge of input clock. It is defined by SITP [1:0] bits in
DFSDM_CHCFGyR1 register.
• Input clock source. External source from DFSDM_CKINy pin or internal from
DFSDM_CKOUT pin. It is defined by SPICKSEL[1:0] field in DFSDM_CHCFGyR1
register.
• Final data right bit-shift. Defines the final data right bit shift to have the result aligned
to a 24-bit value. It is defined by DTRBS[4:0] in DFSDM_CHCFGyR2 register.
• Channel offset per channel. Defines the analog offset of a given serial channel (offset
of connected external modulator). It is defined by OFFSET[23:0] bits in
DFSDM_CHCFGyR2 register.
• short-circuit detector and clock absence per channel enable. To enable or disable
the short-circuit detector (by SCDEN bit) and the clock absence monitoring (by
CKABEN bit) on a given serial channel in register DFSDM_CHCFGyR1.
• Analog watchdog filter and short-circuit detector threshold settings. To configure
channel analog watchdog filter parameters and channel short-circuit detector
parameters. Configurations are defined in DFSDM_AWSCDyR register.
21.3.6 Parallel data inputs
Each input channel provides a register for 16-bit parallel data input (besides serial data
input). Each 16-bit parallel input can be sourced from internal data sources only:
• direct CPU/DMA writing.
The selection for using serial or parallel data input for a given channel is done by field
DATMPX[1:0] of DFSDM_CHCFGyR1 register. In DATMPX[1:0] is also defined the parallel
data source: direct write by CPU/DMA.
Each channel contains a 32-bit data input register DFSDM_CHDATINyR in which it can be
written a 16-bit data. Data are in 16-bit signed format. Those data can be used as input to
the digital filter which is accepting 16-bit parallel data.
If serial data input is selected (DATMPX[1:0] = 0), the DFSDM_CHDATINyR register is write
protected.
Input from memory (direct CPU/DMA write)
The direct data write into DFSDM_CHDATINyR register by CPU or DMA (DATMPX[1:0]=2)
can be used as data input in order to process digital data streams from memory or
peripherals.
Data can be written by CPU or DMA into DFSDM_CHDATINyR register:
1. CPU data write:
Input data are written directly by CPU into DFSDM_CHDATINyR register.
2. DMA data write:
The DMA should be configured in memory-to-memory transfer mode to transfer data
from memory buffer into DFSDM_CHDATINyR register. The destination memory
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