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DocID024597 Rev 3 617/1693

RM0351 Digital filter for sigma delta modulators (DFSDM)

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address is the address of DFSDM_CHDATINyR register. Data are transferred at DMA

transfer speed from memory to DFSDM parallel input.

This DMA transfer is different from DMA used to read DFSDM conversion results. Both

DMA can be used at the same time - first DMA (configured as memory-to-memory

transfer) for input data writings and second DMA (configured as peripheral-to-memory

transfer) for data results reading.

The accesses to DFSDM_CHDATINyR can be either 16-bit or 32-bit wide, allowing to load

respectively one or two samples in one write operation. 32-bit input data register

(DFSDM_CHDATINyR) can be filled with one or two 16-bit data samples, depending on the

data packing operation mode defined in field DATPACK[1:0] of DFSDM_CHCFGyR1

1. Standard mode (DATPACK[1:0]=0):

Only one sample is stored in field INDAT0[15:0] of DFSDM_CHDATINyR register which

is used as input data for channel y. The upper 16 bits (INDAT1[15:0]) are ignored and

write protected. The digital filter must perform one input sampling (from INDAT0[15:0])

to empty data register after it has been filled by CPU/DMA. This mode is used together

with 16-bit CPU/DMA access to DFSDM_CHDATINyR register to load one sample per

write operation.

2. Interleaved mode (DATPACK[1:0]=1):

DFSDM_CHDATINyR register is used as a two sample buffer. The first sample is

stored in INDAT0[15:0] and the second sample is stored in INDAT1[15:0]. The digital

filter must perform two input samplings from channel y to empty DFSDM_CHDATINyR

DFSDM_CHDATINyR register to load two samples per write operation.

3. Dual mode (DATPACK[1:0]=2):

Two samples are written into DFSDM_CHDATINyR register. The data INDAT0[15:0] is

for channel y, the data in INDAT1[15:0] is for channel y+1. The data in INDAT1[15:0] is

automatically copied INDAT0[15:0] of the following (y+1) channel data register

DFSDM_CHDATIN[y+1]R). The digital filters must perform two samplings - one from

channel y and one from channel (y+1) - in order to empty DFSDM_CHDATINyR

registers.

Dual mode setting (DATPACK[1:0]=2) is available only on even channel numbers (y =

0, 2, 4, 6). If odd channel (y = 1, 3, 5, 7) is set to Dual mode then both INDAT0[15:0]

and INDAT1[15:0] parts are write protected for this channel. If even channel is set to

Dual mode then the following odd channel must be set into Standard mode

(DATPACK[1:0]=0) for correct cooperation with even channels.

See Figure 151 for DFSDM_CHDATINyR registers data modes and assignments of data

samples to channels.

ST STM32L4x6 User Manual

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