DocID024597 Rev 3 1381/1685
RM0351 Single Wire Protocol Master Interface (SWPMI)
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40.6 SWPMI registers
Refer to section 1.1 of the reference manual for a list of abbreviations used in register
descriptions.
The peripheral registers can be accessed by words (32-bit).
40.6.1 SWPMI Configuration/Control register (SWPMI_CR)
Address offset: 0x00
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. Res. Res. Res. DEACT Res. Res. Res. Res.
SWP
ACT
LPBK
TXMOD
E
RXMO
DE
TXDMA RXDMA
rw rw rw rw rw rw rw
Bits 31:11 Reserved, must be kept at reset value
Bit 10 DEACT: Single wire protocol master interface deactivate
This bit is used to request the SWP DEACTIVATED state. Setting this bit has the same effect
as clearing the SWPACT, except that a possible incoming RESUME by slave will keep the
SWP in the ACTIVATED state.
Bits 9:6 Reserved, must be kept at reset value
Bit 5 SWPACT: Single wire protocol master interface activate
This bit is used to activate the SWP bus (refer to Section 40.3.2: SWP initialization and
activation).
0: SWPMI_IO is pulled down to ground, SWP bus is switched to DEACTIVATED state
1: SWPMI_IO is released, SWP bus is switched to SUSPENDED state
To be able to set SWPACT bit, DEACT bit must be have been cleared previously.
Bit 4 LPBK: Loopback mode enable
This bit is used to enable the loopback mode
0: Loopback mode is disabled
1: Loopback mode is enabled
Note: This bit cannot be written while SWPACT bit is set.
Bit 3 TXMODE: Transmission buffering mode
This bit is used to choose the transmission buffering mode. This bit is relevant only when
TXDMA bit is set (refer to Table 217: Buffer modes selection for transmission/reception).
0: SWPMI is configured in Single software buffer mode for transmission
1: SWPMI is configured in Multi software buffer mode for transmission.
Note: This bit cannot be written while SWPACT bit is set.
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