DocID024597 Rev 3 191/1693
RM0351 Reset and clock control (RCC)
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6.2.11 ADC clock
The ADC clock is derived from the system clock, or from the PLLSAI1 or the PLLSAI2
output. It can reach 80 MHz and can be divided by the following prescalers values:
1,2,4,6,8,10,12,16,32,64,128 or 256 by configuring the ADC123_CCR register. It is
asynchronous to the AHB clock. Alternatively, the ADC clock can be derived from the AHB
clock of the ADC bus interface, divided by a programmable factor (1, 2 or 4). This
programmable factor is configured using the CKMODE bit fields in the ADC123_CCR.
If the programmed factor is ‘1’, the AHB prescaler must be set to ‘1’.
6.2.12 RTC clock
The RTCCLK clock source can be either the HSE/32, LSE or LSI clock. It is selected by
programming the RTCSEL[1:0] bits in the Backup domain control register (RCC_BDCR).
This selection cannot be modified without resetting the Backup domain. The system must
always be configured so as to get a PCLK frequency greater then or equal to the RTCCLK
frequency for a proper operation of the RTC.
The LSE clock is in the Backup domain, whereas the HSE and LSI clocks are not.
Consequently:
• If LSE is selected as RTC clock:
– The RTC continues to work even if the V
DD
supply is switched off, provided the
V
BAT
supply is maintained.
• If LSI is selected as the RTC clock:
– The RTC state is not guaranteed if the V
DD
supply is powered off.
• If the HSE clock divided by a prescaler is used as the RTC clock:
– The RTC state is not guaranteed if the V
DD
supply is powered off or if the internal
voltage regulator is powered off (removing power from the V
CORE
domain).
6.2.13 Timer clock
The timer clock frequencies are automatically defined by hardware. There are two cases:
1. If the APB prescaler equals 1, the timer clock frequencies are set to the same
frequency as that of the APB domain.
2. Otherwise, they are set to twice (×2) the frequency of the APB domain.
6.2.14 Watchdog clock
If the Independent watchdog (IWDG) is started by either hardware option or software
access, the LSI oscillator is forced ON and cannot be disabled. After the LSI oscillator
temporization, the clock is provided to the IWDG.
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