Advanced encryption standard hardware accelerator (AES) RM0351
740/1693 DocID024597 Rev 3
25.14.2 AES status register (AES_SR)
Address offset: 0x04
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. BUSY WRERR RDERR CCF
rrrr
Bits 31:4 Reserved, must be kept at reset value.
Bit 3 Busy: Busy flag
This bit is set and reset by hardware to indicate that higher priority message can interrupt the current
message during GCM payload phase for encryption mode only
0: GCM suspend mode can perform
1: GCM suspend mode cannot perform
Note: This bit has effect only when GCM algorithm is selected.
Note: This flag has no effect when GCM is configured in GCM init phase, GCM header phase, GCM
payload phase (decryption mode) and GCM final phase.
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