DocID024597 Rev 3 741/1693
RM0351 Advanced encryption standard hardware accelerator (AES)
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Bit 2 WRERR: Write error flag
This bit is set by hardware when an unexpected write operation to the AES_DINR register is detected
(during computation or data output phase). An interrupt is generated if the ERRIE bit has been
previously set in the AES_CR register. This flag has no impact on the AES which continues running
even if WERR is set.
It is cleared by software by setting the ERRC bit in the AES_CR register.
0: No write error detected
1: Write error detected
Note: This Flags has no meaning when:
– Key derivation mode is selected
– GCM init phase
Bit 1 RDERR: Read error flag
This bit is set by hardware when an unexpected read operation from the AES_DOUTR register is
detected (during computation or data input phase). An interrupt is generated if the ERRIE bit has been
previously set in the AES_CR register.This flag has no impact on the AES which continues running
even if RDERR is set.
It is cleared by software by setting the ERRC bit i in the AES_CR register.
0: No read error detected
1: Read error detected
Note: This Flags has no meaning when:
– Key derivation mode is selected
– GCM init phase is selected
– GMAC or CMAC header phase is selected
Bit 0 CCF: Computation complete flag
This bit is set by hardware when the computation is complete. An interrupt is generated if the CCFIE
bit has been previously set in the AES_CR register.
It is cleared by software by setting the CCFC bit in the AES_CR register.
0: Computation is not complete
1: Computation complete
Note: This bit is significant only when DMAOUTEN = 0. It may stay high when DMA_EN = 1.
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