Low-power timer (LPTIM) RM0351
1030/1693 DocID024597 Rev 3
Figure 345. Waveform generation
30.4.9 Register update
The LPTIMx_ARR register and LPTIMx_CMP register are updated immediately after the
APB bus write operation, or at the end of the current period if the timer is already started.
The PRELOAD bit controls how the LPTIMx_ARR and the LPTIMx_CMP registers are
updated:
• When the PRELOAD bit is reset to ‘0’, the LPTIMx_ARR and the LPTIMx_CMP
registers are immediately updated after any write access.
• When the PRELOAD bit is set to ‘1’, the LPTIMx_ARR and the LPTIMx_CMP registers
are updated at the end of the current period, if the timer has been already started.
The APB bus and the LPTIM use different clocks, so there is some latency between the
APB write and the moment when these values are available to the counter comparator.
Within this latency period, any additional write into these registers must be avoided.
The ARROK flag and the CMPOK flag in the LPTIMx_ISR register indicate when the write
operation is completed to respectively the LPTIMx_ARR register and the LPTIMx_CMP
register.
After a write to the LPTIMx_ARR register or the LPTIMx_CMP register, a new write
operation to the same register can only be performed when the previous write operation is
completed. Any successive write before respectively the ARROK flag or the CMPOK flag be
set, will lead to unpredictable results.
069
$55
&RPSDUH
3:0
2QHVKRW
6HWRQFH
3:0
2QHVKRW
6HWRQFH
3RO
3RO
To Next Page
Loading...
Need help?
General
