DocID024597 Rev 3 1017/1693
RM0351 Basic timers (TIM6/TIM7)
1022
Figure 339. Control circuit in normal mode, internal clock divided by 1
29.3.5 Debug mode
When the microcontroller enters the debug mode (Cortex
®
-M4 core - halted), the TIMx
counter either continues to work normally or stops, depending on the DBG_TIMx_STOP
configuration bit in the DBG module. For more details, refer to Section 44.16.2: Debug
support for timers, RTC, watchdog, bxCAN and I2C.
29.4 TIM6/TIM7 registers
Refer to Section 1.1 on page 61 for a list of abbreviations used in register descriptions.
The peripheral registers can be accessed by half-words (16-bit) or words (32-bit).
29.4.1 TIM6/TIM7 control register 1 (TIMx_CR1)
Address offset: 0x00
Reset value: 0x0000
,QWHUQDOFORFN
&RXQWHUFORFN &.B&17 &.B36&
&RXQWHUUHJLVWHU
&(1 &17B(1
8*
&17B,1,7
069
1514131211109876543210
Res Res Res Res
UIF
RE-
MAP
Res Res Res ARPE Res Res Res OPM URS UDIS CEN
rw rw rw rw rw rw
Bits 15:12 Reserved, must be kept at reset value.
Bit 11 UIFREMAP: UIF status bit remapping
0: No remapping. UIF status bit is not copied to TIMx_CNT register bit 31.
1: Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31.
Bits 10:8 Reserved, must be kept at reset value.
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