ST STM32L4x6

DocID024597 Rev 3 145/1693
RM0351 Power control (PWR)
178
Table 20. Functionalities depending on the working mode
(1)
Peripheral Run Sleep
Low-
power
run
Low-
power
sleep
Stop 0/1 Stop 2 Standby Shutdown
VBAT
-
Wakeup capability
-
Wakeup capability
-
Wakeup capability
-
Wakeup capability
CPU Y - Y - - ------ --
Flash memory (up to 1 MB) O
(2)
O
(2)
O
(2)
O
(2)
- --------
SRAM1 (up to 96 KB) Y Y
(3)
YY
(3)
Y -Y---- --
SRAM2 (32 KB) Y Y
(3)
YY
(3)
Y -Y-O
(4)
-- --
FSMC OOOO-
------ --
QUADSPI O O O O -
------ --
Backup Registers Y Y Y Y Y
-Y-Y-Y -Y
Brown-out reset (BOR) Y Y Y Y Y
YYYYY- --
Programmable Voltage
Detector (PVD)
OOOOOOOO- -- --
Peripheral Voltage Monitor
(PVMx; x=1,2,3,4)
OOOOO
OOO- -- --
DMA O O O O - ------ --
High Speed Internal (HSI16) O O O O
(5)
-
(5)
---- --
High Speed External (HSE) O O O O - --------
Low Speed Internal (LSI) O O O O O -O-O----
Low Speed External (LSE) O O O O O -O-O-O-O
Multi-Speed Internal (MSI) O O O O -
------ --
Clock Security System
(CSS)
OOOO-
------ --
Clock Security System on
LSE
OOOOO
OOOOO- --
RTC / Auto wakeup O O O O O OOOOOO OO
Number of RTC Tamper
pins
33333O3O3O3 O3
LCD O O O O O OOO- -- --
USB OTG FS O
(8)
O
(8)
---O- ---- --
USARTx (x=1,2,3,4,5) O O O O O
(6)
O
(6)
- ---- --
Low-power UART
(LPUART)
OOOOO
(6)
O
(6)
O
(6)
O
(6)
- -- --