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RM0351 Peripherals interconnect matrix
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9.3.3 From ADC (ADC1/ADC2/ADC3) to timer (TIM1/TIM8)
Purpose
ADC1/ADC2/ADC3 can provide trigger event through watchdog signals to advanced-control
timers (TIM1/TIM8).
A description of the ADC analog watchdog setting is provided in: Section 16.3.28: Analog
window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH, AWD2CH, AWD3CH,
AWD_HTx, AWD_LTx, AWDx).
Trigger settings on the timer are provided in: Section 26.3.4: External trigger input.
Triggering signals
The output (from ADC) is on signals ADCn_AWDx_OUT n = 1, 2, 3 (for ADC1, 2, 3) x = 1, 2,
3 (3 watchdog per ADC) and the input (to timer) on signal TIMx_ETR (external trigger).
Active power mode
Run, Sleep, Low-power run, Low-power sleep.
9.3.4 From timer (TIM2/TIM4/TIM5/TIM6/TIM7/TIM8) and EXTI to DAC
(DAC1/DAC2)
Purpose
General-purpose timers (TIM2/TIM4/TIM5), basic timers (TIM6, TIM7), advanced-control
timers (TIM8) and EXTI can be used as triggering event to start a DAC conversion.
Triggering signals
The output (from timer) is on signal TIMx_TRGO directly connected to corresponding DAC
inputs.
Selection of input triggers on DAC is provided in Section 17.3.6: DAC trigger selection
(single and dual mode).
Active power mode
Run, Sleep, Low-power run, Low-power sleep.
9.3.5 From timer (TIM1/TIM3/TIM4/TIM6/TIM7/TIM8/TIM16) and EXTI to
DFSDM
Purpose
General-purpose timers (TIM3/TIM4), basic timers (TIM6/TIM7), advanced-control timers
(TIM1/TIM8), general-purpose timer (TIM16) and EXTI can be used to generate a triggering
event on DFSDM module (on each possible data block
DFSDM0/DFSDM1/DFSDM2/DFSDM3) and start an ADC conversion.
DFSDM triggered conversion feature is described in: Section 21.3.15: Launching
conversions.
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