Peripherals interconnect matrix RM0351
288/1693 DocID024597 Rev 3
The modes of synchronization are detailed in:
• Section 26.3.26: Timer synchronization for advanced-control timers (TIM1/TIM8)
• Section 27.3.18: Timers and external trigger synchronization for general-purpose
timers (TIM2/TIM3/TIM4/TIM5)
• Section 28.4.17: External trigger synchronization (TIM15 only) for general-purpose
timer (TIM15)
Triggering signals
The output (from Master) is on signal TIMx_TRGO (and TIMx_TRGO2 for TIM1/TIM8)
following a configurable timer event.
The input (to slave) is on signals TIMx_ITR0/ITR1/ITR2/ITR3
The input and output signals for TIM1/TIM8 are shown in Figure 188: Advanced-control
timer block diagram.
The possible master/slave connections are given in:
• Table 148: TIMx internal trigger connection
• Table 153: TIMx internal trigger connection
• Table 156: TIMx Internal trigger connection
Active power mode
Run, Sleep, Low-power run, Low-power sleep.
9.3.2 From timer (TIM1/TIM2/TIM3/TIM4/TIM6/TIM8/TIM15) and EXTI to ADC
(ADC1/ADC2/ADC3)
Purpose
General-purpose timers (TIM2/TIM3/TIM4), basic timer (TIM6), advanced-control timers
(TIM1/TIM8), general-purpose timer (TIM15) and EXTI can be used to generate an ADC
triggering event.
TIMx synchronization is described in: Section 26.3.27: ADC synchronization (TIM1/TIM8).
ADC synchronization is described in: Section 16.3.18: Conversion on external trigger and
trigger polarity (EXTSEL, EXTEN, JEXTSEL, JEXTEN).
Triggering signals
The output (from timer) is on signal TIMx_TRGO, TIMx_TRGO2 or TIMx_CCx event.
The input (to ADC) is on signal EXT[15:0], JEXT[15:0].
The connection between timers and ADCs is provided in:
• Table 88: ADC1, ADC2 and ADC3 - External triggers for regular channels
• Table 89: ADC1, ADC2 and ADC3 - External trigger for injected channels
Active power mode
Run, Sleep, Low-power run, Low-power sleep.
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