DocID024597 Rev 3 63/1693
RM0351 System and memory overview
64
Figure 1. System architecture
2.1.1 S0: I-bus
This bus connects the instruction bus of the Cortex
®
-M4 core to the BusMatrix. This bus is
used by the core to fetch instructions. The targets of this bus are the internal Flash memory,
SRAM1, SRAM2 and external memories through FMC or QUADSPI.
2.1.2 S1: D-bus
This bus connects the data bus of the Cortex
®
-M4 core to the BusMatrix. This bus is used
by the core for literal load and debug access. The targets of this bus are the internal Flash
memory, SRAM1, SRAM2 and external memories through FMC or QUADSPI.
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