Digital-to-analog converter (DAC) RM0351
568/1693 DocID024597 Rev 3
17.5.15 DAC calibration control register (DAC_CCR)
Address offset: 0x38
Reset value: 0x00XX 00XX
17.5.16 DAC mode control register (DAC_MCR)
Address offset: 0x3C
Reset value: 0x0000 0000
Bit 14 CAL_FLAG1: DAC Channel 1 calibration offset status
This bit is set and cleared by hardware
0: calibration trimming value is greater than the offset correction value
1: calibration trimming value is lower than the offset correction value
Bit 13 DMAUDR1: DAC channel1 DMA underrun flag
This bit is set by hardware and cleared by software (by writing it to 1).
0: No DMA underrun error condition occurred for DAC channel1
1: DMA underrun error condition occurred for DAC channel1 (the currently selected trigger is
driving DAC channel1 conversion at a frequency higher than the DMA service capability rate)
Bits 12:0 Reserved, must be kept at reset value.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. OTRIM2[4:0]
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1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. OTRIM1[4:0]
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Bits 31:21 Reserved, must be kept at reset value.
Bits 20:16 OTRIM2[4:0]: DAC Channel 2 offset trimming value
Bits 15:5 Reserved, must be kept at reset value.
Bits 4:0 OTRIM1[4:0]: DAC Channel 1 offset trimming value
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. MODE2[2:0]
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1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. MODE1[2:0]
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