DocID024597 Rev 3 367/1693
RM0351 Flexible static memory controller (FSMC)
399
Muxed mode - multiplexed asynchronous access to NOR Flash memory
Figure 42. Muxed read access waveforms
Table 69. FMC_BWTRx bit fields
Bit number Bit name Value to set
31:30 Reserved 0x0
29-28 ACCMOD 0x3
27-24 DATLAT Don’t care
23-20 CLKDIV Don’t care
19-16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK)
15-8 DATAST
Duration of the second access phase (DATAST + 1 HCLK cycles) for
write accesses.
7-4 ADDHLD
Duration of the middle phase of the write access (ADDHLD HCLK
cycles)
3-0 ADDSET
Duration of the first access phase (ADDSET HCLK cycles) for write
accesses. Minimum value for ADDSET is 1.
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