DocID024597 Rev 3 401/1693
RM0351 Quad-SPI interface (QUADSPI)
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The QUADSPI uses 6 signals to interface with a Flash memory:
– CLK - Clock output
– BK1_IO0/SO - Bidirectional IO in dual/quad modes or serial output in single mode
– BK1_IO1/SI - Bidirectional IO in dual/quad modes or serial input in single mode
– BK1_IO2 - Bidirectional IO in quad mode
– BK1_IO3 - Bidirectional IO in quad mode
– BK1_nCS - Chip select output (active low)
15.3.2 QUADSPI Command sequence
The QUADSPI communicates with the Flash memory using commands. Each command
can include 5 phases: instruction, address, alternate byte, dummy, data. Any of these
phases can be configured to be skipped, but at least one of the instruction, address,
alternate byte, or data phase must be present.
nCS falls before the start of each command and rises again after each command finishes.
Figure 52. An example of a read command in quad mode
Instruction phase
During this phase, an 8-bit instruction, configured in INSTRUCTION field of
QUADSPI_CCR[7:0] register, is sent to the Flash memory, specifying the type of operation
to be performed.
Though most Flash memories can receive instructions only one bit at a time from the
IO0/SO signal (single SPI mode), the instruction phase can optionally send 2 bits at a time
(over IO0/IO1 in dual SPI mode) or 4 bits at a time (over IO0/IO1/IO2/IO3 in quad SPI
mode). This can be configured using the IMODE[1:0] field of QUADSPI_CCR[9:8] register.
When IMODE = 00, the instruction phase is skipped, and the command sequence starts
with the address phase, if present.
Address phase
In the address phase, 1-4 bytes are sent to the Flash memory to indicate the address of the
operation. The number of address bytes to be sent is configured in the ADSIZE[1:0] field of
QUADSPI_CCR[13:12] register. In indirect and automatic-polling modes, the address bytes
to be sent are specified in the ADDRESS[31:0] field of QUADSPI_AR register, while in
memory-mapped mode the address is given directly via the AHB (from the Cortex
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or from
a DMA).
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