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RM0351 Analog-to-digital converters (ADC)
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16.3.3 Clocks
Dual clock domain architecture
The dual clock-domain architecture means that the ADCs clock is independent from the
AHB bus clock.
The input clock is the same for the three ADCs and can be selected between two different
clock sources (see Figure 59: ADC clock scheme):
a) The ADC clock can be a specific clock source, coming from the system clock, the
PLLSAI1 or the PLLSAI2.
It can be configured in the RCC to deliver up to 80 MHz (PLL output). Refer to
RCC Section for more information on how to generate ADC dedicated clock.
To select this scheme, bits CKMODE[1:0] of the ADCx_CCR register must be
reset.
b) The ADC clock can be derived from the AHB clock of the ADC bus interface,
divided by a programmable factor (1, 2 or 4). In this mode, a programmable divider
factor can be selected (/1, 2 or 4 according to bits CKMODE[1:0]).
To select this scheme, bits CKMODE[1:0] of the ADCx_CCR register must be
different from “00”.
Note: For option b), a prescaling factor of 1 (CKMODE[1:0]=01) can be used only if the AHB
prescaler is set to 1 (HPRE[3:0] = 0xxx in RCC_CFGR register).
Option a) has the advantage of reaching the maximum ADC clock frequency whatever the
AHB clock scheme selected. The ADC clock can eventually be divided by the following ratio:
1, 2, 4, 6, 8, 12, 16, 32, 64, 128, 256; using the prescaler configured with bits PRESC[3:0] in
the ADCx_CCR register.
Option b) has the advantage of bypassing the clock domain resynchronizations. This can be
useful when the ADC is triggered by a timer and if the application requires that the ADC is
precisely triggered without any uncertainty (otherwise, an uncertainty of the trigger instant is
added by the resynchronizations between the two clock domains).
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