ST STM32L4x6

DocID024597 Rev 3 359/1693
RM0351 Flexible static memory controller (FSMC)
399
Mode 2/B - NOR Flash
Figure 35. Mode2 and mode B read access waveforms
Table 60. FMC_BWTRx bit fields
Bit number Bit name Value to set
31:30 Reserved 0x0
29-28 ACCMOD 0x0
27-24 DATLAT Don’t care
23-20 CLKDIV Don’t care
19-16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK)
15-8 DATAST
Duration of the second access phase (DATAST HCLK cycles) for write
accesses.
7-4 ADDHLD Don’t care
3-0 ADDSET
Duration of the first access phase (ADDSET HCLK cycles) for write
accesses.
Minimum value for ADDSET is 0.
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