Controller area network (bxCAN) RM0351
1480/1693 DocID024597 Rev 3
42.9.3 CAN mailbox registers
This section describes the registers of the transmit and receive mailboxes. Refer to
Section 42.7.5: Message storage on page 1464 for detailed register mapping.
Transmit and receive mailboxes have the same registers except:
• The FMI field in the CAN_RDTxR register.
• A receive mailbox is always write protected.
• A transmit mailbox is write-enabled only while empty, corresponding TME bit in the
CAN_TSR register set.
There are 3 TX Mailboxes and 2 RX Mailboxes. Each RX Mailbox allows access to a 3 level
depth FIFO, the access being offered only to the oldest received message in the FIFO.
Each mailbox consist of 4 registers.
Bit 31 SILM: Silent mode (debug)
0: Normal operation
1: Silent Mode
Bit 30 LBKM
: Loop back mode (debug)
0: Loop Back Mode disabled
1: Loop Back Mode enabled
Bits 29:26 Reserved, must be kept at reset value.
Bits 25:24 SJW[1:0]
: Resynchronization jump width
These bits define the maximum number of time quanta the CAN hardware is allowed to
lengthen or shorten a bit to perform the resynchronization.
t
RJW
= t
q
x (SJW[1:0] + 1)
Bit 23 Reserved, must be kept at reset value.
Bits 22:20 TS2[2:0]: Time segment 2
These bits define the number of time quanta in Time Segment 2.
t
BS2
= t
q
x (TS2[2:0] + 1)
Bits 19:16 TS1[3:0]
: Time segment 1
These bits define the number of time quanta in Time Segment 1
t
BS1
= t
q
x (TS1[3:0] + 1)
For more information on bit timing, please refer to Section 42.7.7: Bit timing on page 1466.
Bits 15:10 Reserved, must be kept at reset value.
Bits 9:0 BRP[9:0]
: Baud rate prescaler
These bits define the length of a time quanta.
t
q
= (BRP[9:0]+1) x t
PCLK
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