DocID024597 Rev 3 449/1693
RM0351 Analog-to-digital converters (ADC)
540
Note: The regular trigger selection cannot be changed on-the-fly.
The injected trigger selection can be anticipated and changed on-the-fly. Refer to
Section 16.3.21: Queue of context for injected conversions on page 453
Each ADC master shares the same input triggers with its ADC slave as described in
Figure 70.
Figure 70. Triggers are shared between ADC master and ADC slave
Table 88 to Table 89 give all the possible external triggers of the three ADCs for regular and
injected conversion.
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Table 88. ADC1, ADC2 and ADC3 - External triggers for regular channels
Name Source Type EXTSEL[3:0]
EXT0 TIM1_CC1 event Internal signal from on-chip timers 0000
EXT1 TIM1_CC2 event Internal signal from on-chip timers 0001
EXT2 TIM1_CC3 event Internal signal from on-chip timers 0010
EXT3 TIM2_CC2 event Internal signal from on-chip timers 0011
EXT4 TIM3_TRGO event Internal signal from on-chip timers 0100
EXT5 TIM4_CC4 event Internal signal from on-chip timers 0101
EXT6 EXTI line 11 External pin 0110
EXT7 TIM8_TRGO event Internal signal from on-chip timers 0111
EXT8 TIM8_TRGO2 event Internal signal from on-chip timers 1000
EXT9 TIM1_TRGO event Internal signal from on-chip timers 1001