Analog-to-digital converters (ADC) RM0351
470/1693 DocID024597 Rev 3
1. Wait until JEOS=1 (no more conversions are restarted)
2. Clear JEOS,
3. Set ADSTP=1
4. Read the regular data.
If this procedure is not respected, a new regular sequence can re-start if JEOS is cleared
after ADSTP has been set.
In AUTDLY mode, a hardware regular trigger event is ignored if it occurs during an already
ongoing regular sequence or during the delay that follows the last regular conversion of the
sequence. It is however considered pending if it occurs after this delay, even if it occurs
during an injected sequence of the delay that follows it. The conversion then starts at the
end of the delay of the injected sequence.
In AUTDLY mode, a hardware injected trigger event is ignored if it occurs during an already
ongoing injected sequence or during the delay that follows the last injected conversion of
the sequence.
Figure 93. AUTODLY=1, regular conversion in continuous mode, software trigger
1. AUTDLY=1
2. Regular configuration: EXTEN=0x0 (SW trigger), CONT=1, CHANNELS = 1,2,3
3. Injected configuration DISABLED
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