DocID024597 Rev 3 989/1693
RM0351 General-purpose timers (TIM15/16/17)
1009
28.6 TIM16&TIM17 registers
Refer to Section 1.1 on page 61 for a list of abbreviations used in register descriptions.
28.6.1 TIM16&TIM17 control register 1 (TIMx_CR1)
Address offset: 0x00
Reset value: 0x0000
1514131211109876543210
Res Res Res Res
UIF
REM-
AP
Res CKD[1:0] ARPE Res Res Res OPM URS UDIS CEN
rw rw rw rw rw rw rw rw
Bits 15:12 Reserved, must be kept at reset value.
Bit 11 UIFREMAP: UIF status bit remapping
0: No remapping. UIF status bit is not copied to TIMx_CNT register bit 31.
1: Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31.
Bit 10 Reserved, must be kept at reset value.
Bits 9:8 CKD[1:0]: Clock division
This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the
dead-time and sampling clock (t
DTS
)used by the dead-time generators and the digital filters
(TIx),
00: t
DTS
=t
CK_INT
01: t
DTS
=2*t
CK_INT
10: t
DTS
=4*t
CK_INT
11: Reserved, do not program this value
Bit 7 ARPE: Auto-reload preload enable
0: TIMx_ARR register is not buffered
1: TIMx_ARR register is buffered
Bits 6:4 Reserved, must be kept at reset value.
Bit 3 OPM: One pulse mode
0: Counter is not stopped at update event
1: Counter stops counting at the next update event (clearing the bit CEN)
Bit 2 URS: Update request source
This bit is set and cleared by software to select the UEV event sources.
0: Any of the following events generate an update interrupt or DMA request if enabled.
These events can be:
– Counter overflow/underflow
– Setting the UG bit
– Update generation through the slave mode controller
1: Only counter overflow/underflow generates an update interrupt or DMA request if
enabled.
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