ST STM32L4x6 User Manual

DocID024597 Rev 3 227/1693
RM0351 Reset and clock control (RCC)
253
6.4.18 AHB3 peripheral clock enable register(RCC_AHB3ENR)
Address offset: 0x50
Reset value: 0x00000 0000
Access: no wait state, word, half-word and byte access
Note: When the peripheral clock is not active, the peripheral registers read or write access is not
supported.
6.4.19 APB1 peripheral clock enable register 1 (RCC_APB1ENR1)
Address: 0x58
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
Bit 2 GPIOCEN: IO port C clock enable
Set and cleared by software.
0: IO port C clock disabled
1: IO port C clock enabled
Bit 1 GPIOBEN: IO port B clock enable
Set and cleared by software.
0: IO port B clock disabled
1: IO port B clock enabled
Bit 0 GPIOAEN: IO port A clock enable
Set and cleared by software.
0: IO port A clock disabled
1: IO port A clock enabled
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109 8 76543210
Res. Res. Res. Res. Res. Res. Res.
QSPI
EN
Res. Res. Res. Res. Res. Res. Res.
FMC
EN
rw rw
Bits 31:9 Reserved, must be kept at reset value.
Bit 8 QSPIEN Quad SPI memory interface clock enable
Set and cleared by software.
0: QUADSPI clock disable
1: QUADSPI clock enable
Bits 7:1 Reserved, must be kept at reset value.
Bit 0 FMCEN: Flexible memory controller clock enable
Set and cleared by software.
0: FMC clock disable
1: FMC clock enable

ST STM32L4x6 Specifications

General

Brand	ST
Model	STM32L4x6
Category	Microcontrollers
Language	English