DocID024597 Rev 3 557/1693
RM0351 Digital-to-analog converter (DAC)
573
Simultaneous trigger with single triangle generation
To configure the DAC in this conversion mode, the following sequence is required:
• Set the two DAC channel trigger enable bits TEN1 and TEN2
• Configure the same trigger source for both DAC channels by setting the same value in
the TSEL1[2:0] and TSEL2[2:0] bits
• Configure the two DAC channel WAVEx[1:0] bits as “1x” and the same maximum
amplitude value using the MAMPx[3:0] bits
• Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD,
DAC_DHR12LD or DAC_DHR8RD)
When a trigger arrives, the DAC channel1 triangle counter, with the same triangle
amplitude, is added to the DHR1 register and the sum is transferred into DAC_DOR1 (three
APB1 clock cycles later). The DAC channel1 triangle counter is then updated.
At the same time, the DAC channel2 triangle counter, with the same triangle amplitude, is
added to the DHR2 register and the sum is transferred into DAC_DOR2 (three APB1 clock
cycles later). The DAC channel2 triangle counter is then updated.
17.3.13 Simultaneous trigger with different triangle generation
To configure the DAC in this conversion mode, the following sequence is required:
• Set the two DAC channel trigger enable bits TEN1 and TEN2
• Configure the same trigger source for both DAC channels by setting the same value in
the TSEL1[2:0] and TSEL2[2:0] bits
• Configure the two DAC channel WAVEx[1:0] bits as “1x” and set different maximum
amplitude values in the MAMP1[3:0] and MAMP2[3:0] bits
• Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD,
DAC_DHR12LD or DAC_DHR8RD)
When a trigger arrives, the DAC channel1 triangle counter, with a triangle amplitude
configured by MAMP1[3:0], is added to the DHR1 register and the sum is transferred into
DAC_DOR1 (three APB clock cycles later). Then the DAC channel1 triangle counter is
updated.
At the same time, the DAC channel2 triangle counter, with a triangle amplitude configured
by MAMP2[3:0], is added to the DHR2 register and the sum is transferred into DAC_DOR2
(three APB1 clock cycles later). Then the DAC channel2 triangle counter is updated.
17.4 DAC low power modes
Table 105. Effect of low-power modes on DAC
Mode Description
Sleep No effect, DAC used with DMA
Low-power run No effect.
Low-power sleep No effect. DAC used with DMA.
Stop 0 / Stop 1
DAC remains active with a static value, if sample and hold mode is
selected using LSI clock
Stop 2
The DAC registers content is kept. The DAC must be disabled before
entering Stop 2.
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