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RM0351 Liquid crystal display controller (LCD)
690
22.4 LCD low-power modes
the LCD controller can be displayed in Stop mode or can be fully disabled to reduce power
consumption.
22.5 LCD interrupts
The table below gives the list of LCD interrupt requests.
Start of frame (SOF)
The LCD start of frame interrupt is executed if the SOFIE (start of frame interrupt enable) bit
is set (see Section 22.6.2: LCD frame control register (LCD_FCR)). SOF is cleared by
writing the SOFC bit to 1 in the LCD_CLR register when executing the corresponding
interrupt handling vector.
Update display done (UDD)
The LCD update display interrupt is executed if the UDDIE (update display done interrupt
enable) bit is set (see Section 22.6.2: LCD frame control register (LCD_FCR)). UDD is
cleared by writing the UDDC bit to 1 in the LCD_CLR register when executing the
corresponding interrupt handling vector.
Depending on the product implementation, all these interrupts events can either share the
same interrupt vector (LCD global interrupt), or be grouped into 2 interrupt vectors (LCD
SOF interrupt and LCD UDD interrupt). Refer to the
Table 42: STM32L4x6 vector table for
details.
In order to enable the LCD interrupts, the following sequence is required:
Table 131. LCD behavior in low-power modes
Mode Description
Sleep No effect. LCD interrupt causes the device to exit the Sleep mode.
Low-power run No effect.
Low-power sleep
No effect. LCD interrupt causes the device to exit the Low-power sleep
mode.
Stop 0
No effect. LCD interrupt causes the device to exit the Stop mode.Stop 1
Stop 2
Standby
The LCD peripheral is powered down and must be reinitialized after exiting
Standby or Shutdown mode.
Shutdown
Table 132. LCD interrupt requests
Interrupt event Event flag
Event flag/Interrupt
clearing method
Interrupt enable
control bit
Start Of Frame (SOF) SOF Write SOFC =1 SOFIE
Update Display Done (UDD) UDD Write UDDC = 1 UDDIE
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