ST STM32L4x6 User Manual

System configuration controller (SYSCFG) RM0351
274/1693 DocID024597 Rev 3
Note: When the FSMC is remapped at address 0x0000 0000, only the first two regions of Bank 1
memory controller (Bank1 NOR/PSRAM 1 and NOR/PSRAM 2) can be remapped. In remap
mode, the CPU can access the external memory via ICode bus instead of System bus
which boosts up the performance.
8.2.2 SYSCFG configuration register 1 (SYSCFG_CFGR1)
Address offset: 0x04
Reset value: 0x7C00 0001
Bit 8 FB_MODE: Flash Bank mode selection
0: Flash Bank 1 mapped at 0x0800 0000 (and aliased @0x0000 0000) and Flash Bank 2
mapped at 0x0808 0000 (and aliased at 0x0008 0000)
1: Flash Bank2 mapped at 0x0800 0000 (and aliased @0x0000 0000) and Flash Bank 1
mapped at 0x0808 0000 (and aliased at 0x0008 0000)
Bits 7:3 Reserved, must be kept at reset value.
Bits 2:0 MEM_MODE: Memory mapping selection
These bits control the memory internal mapping at address 0x0000 0000. These bits are
used to select the physical remap by software and so, bypass the BOOT pin and the option
bit setting. After reset these bits take the value selected by BOOT0 pin and BOOT1 option
bit.
000: Main Flash memory mapped at 0x00000000.
001: System Flash memory mapped at 0x00000000.
010: FMC bank 1 (NOR/PSRAM 1 and 2) mapped at 0x00000000.
011: SRAM1 mapped at 0x00000000.
100: Reserved
101: Reserved
110: QUADSPI memory mapped at 0x00000000.
111: Reserved
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FPU_IE[5..0] Res Res Res
I2C3_
FMP
I2C2_
FMP
I2C1_
FMP
I2C_
PB9_
FMP
I2C_
PB8_
FMP
I2C_
PB7_
FMP
I2C_
PB6_
FMP
rw rw rw rw rw rw rw rw rw rw rw rw rw
1514131211109876543210
Res Res Res Res Res Res Res
BOOST
EN
Res Res Res Res Res Res Res FWDIS
rw rc_w0

ST STM32L4x6 Specifications

General

Brand	ST
Model	STM32L4x6
Category	Microcontrollers
Language	English