Inter-integrated circuit (I2C) interface RM0351
1110/1693 DocID024597 Rev 3
The I2C is clocked by an independent clock source which allows to the I2C to operate
independently from the PCLK frequency.
This independent clock source can be selected for either of the following three clock
sources:
• PCLK1: APB1 clock (default value)
• HSI16: internal 16 MHz RC oscillator
• SYSCLK: system clock
Refer to Section 6: Reset and clock control (RCC) for more details.
I2C I/Os support 20 mA output current drive for Fast-mode Plus operation. This is enabled
by setting the driving capability control bits for SCL and SDA in Section 8.2.3: SYSCFG
external interrupt configuration register 1 (SYSCFG_EXTICR1)
35.4.2 I2C clock requirements
The I2C kernel is clocked by I2CCLK.
The I2CCLK period t
I2CCLK
must respect the following conditions:
t
I2CCLK < (tLOW - tfilters ) / 4 and
t
I2CCLK < tHIGH
with:
t
LOW: SCL low time and tHIGH : SCL high time
t
filters:
when enabled, sum of the delays brought by the analog filter and by the digital filter.
Analog filter delay is maximum 260 ns. Digital filter delay is DNF x t
I2CCLK
.
The PCLK clock period t
PCLK
must respect the following condition:
t
PCLK < 4/3 tSCL
with t
SCL: SCL period
Caution: When the I2C kernel is clocked by PCLK. PCLK must respect the conditions for t
I2CCLK
.
35.4.3 Mode selection
The interface can operate in one of the four following modes:
• Slave transmitter
• Slave receiver
• Master transmitter
• Master receiver
By default, it operates in slave mode. The interface automatically switches from slave to
master when it generates a START condition, and from master to slave if an arbitration loss
or a STOP generation occurs, allowing multimaster capability.
Communication flow
In Master mode, the I2C interface initiates a data transfer and generates the clock signal. A
serial data transfer always begins with a START condition and ends with a STOP condition.
Both START and STOP conditions are generated in master mode by software.
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