Direct memory access controller (DMA) RM0351
306/1693 DocID024597 Rev 3
Table 40. Summary of the DMA2 requests for each channel
Request.
number
Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7
0 - - ADC1 ADC2 ADC3 - -
1 SAI1_A SAI1_B SAI2_A SAI2_B - SAI1_A SAI1_B
2 UART5_TX UART5_RX UART4_TX - UART4_RX USART1_TX USART1_RX
3 SPI3_RX SPI3_TX -
TIM6_UP
DAC1
TIM7_UP
DAC2
- QUADSPI
4 SWPMI_RX SWPMI_TX SPI1_RX SPI1_TX - LPUART_TX LPUART_RX
5
TIM5_CH4
TIM5_TRIG
TIM5_COM
TIM5_CH3
TIM5_UP
- TIM5_CH2 TIM5_CH1 I2C1_RX I2C1_TX
6 AES_IN AES_OUT AES_OUT - AES_IN - -
7
TIM8_CH3
TIM8_UP
TIM8_CH4
TIM8_TRIG
TIM8_COM
- SDMMC1 SDMMC1 TIM8_CH1 TIM8_CH2
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