Flexible static memory controller (FSMC) RM0351
364/1693 DocID024597 Rev 3
1 MUXEN 0x0
0 MBKEN 0x1
Table 64. FMC_BCRx bit fields (continued)
Bit number Bit name Value to set
Table 65. FMC_BTRx bit fields
Bit number Bit name Value to set
31:30 Reserved 0x0
29-28 ACCMOD 0x2
27-24 DATLAT 0x0
23-20 CLKDIV 0x0
19-16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK)
15-8 DATAST
Duration of the second access phase (DATAST HCLK cycles) for
read accesses.
7-4 ADDHLD Don’t care
3-0 ADDSET
Duration of the first access phase (ADDSET HCLK cycles) for read
accesses. Minimum value for ADDSET is 0.
Table 66. FMC_BWTRx bit fields
Bit number Bit name Value to set
31:30 Reserved 0x0
29-28 ACCMOD 0x2
27-24 DATLAT Don’t care
23-20 CLKDIV Don’t care
19-16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK)
15-8 DATAST
Duration of the second access phase (DATAST HCLK cycles) for
write accesses.
7-4 ADDHLD Don’t care
3-0 ADDSET
Duration of the first access phase (ADDSET HCLK cycles) for write
accesses. Minimum value for ADDSET is 0.