Reset and clock control (RCC) RM0351
230/1693 DocID024597 Rev 3
6.4.20 APB1 peripheral clock enable register 2 (RCC_APB1ENR2)
Address offset: 0x5C
Reset value: 0x00000 0000
Access: no wait state, word, half-word and byte access
Note: When the peripheral clock is not active, the peripheral registers read or write access is not
supported.
Bit 3 TIM5EN: TIM5 timer clock enable
Set and cleared by software.
0: TIM5 clock disabled
1: TIM5 clock enabled
Bit 2 TIM4EN: TIM4 timer clock enable
Set and cleared by software.
0: TIM4 clock disabled
1: TIM4 clock enabled
Bit 1 TIM3EN: TIM3 timer clock enable
Set and cleared by software.
0: TIM3 clock disabled
1: TIM3 clock enabled
Bit 0 TIM2EN: TIM2 timer clock enable
Set and cleared by software.
0: TIM2 clock disabled
1: TIM2 clock enabled
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
LPTIM2
EN
Res. Res.
SWP
MI1
EN
Res.
LP
UART1
EN
rw rw
Bits 31:6 Reserved, must be kept at reset value.
Bit 5 LPTIM2EN Low power timer 2 clock enable
Set and cleared by software.
0: LPTIM2 clock disable
1: LPTIM2 clock enable
Bits 4:3 Reserved, must be kept at reset value.
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