DocID024597 Rev 3 335/1693
RM0351 Extended interrupts and events controller (EXTI)
336
12.5.12 Pending register 2 (EXTI_PR2)
Address offset: 0x34
Reset value: undefined
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109 8 765432 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. PIF38 PIF37 PIF36 PIF35 Res. Res. Res.
rc_w1 rc_w1 rc_w1 rc_w1
Bits 31:8 Reserved, must be kept at reset value.
Bit 7 PIFx: Pending interrupt flag on line x (x = 35 to 38)
0: No trigger request occurred
1: Selected trigger request occurred
This bit is set when the selected edge event arrives on the interrupt line. This bit
is cleared by writing a ‘1’ into the bit.
Bits 2:0 Reserved, must be kept at reset value.
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