To Next Page

To Previous Page

System window watchdog (WWDG) RM0351

1060/1693 DocID024597 Rev 3

33.4 WWDG registers

Refer to Section 1.1 on page 61 for a list of abbreviations used in register descriptions.

The peripheral registers can be accessed by half-words (16-bit) or words (32-bit).

33.4.1 Control register (WWDG_CR)

Address offset: 0x00

Reset value: 0x0000 007F

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

1514131211109876543210

Res. Res. Res. Res. Res. Res. Res. Res. WDGA T[6:0]

rs rw

Bits 31:8 Reserved, must be kept at reset value.

Bit 7 WDGA: Activation bit

This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the

watchdog can generate a reset.

0: Watchdog disabled

1: Watchdog enabled

Bits 6:0 T[6:0]: 7-bit counter (MSB to LSB)

These bits contain the value of the watchdog counter. It is decremented every (4096 x

WDGTB

[1:0]

) PCLK cycles. A reset is produced when it rolls over from 0x40 to 0x3F (T6

becomes cleared).

ST STM32L4x6 User Manual

Questions and Answers: