Universal synchronous asynchronous receiver transmitter (USART) RM0351
1216/1693 DocID024597 Rev 3
Figure 403. Reception using DMA
Error flagging and interrupt generation in multibuffer communication
In multibuffer communication if any error occurs during the transaction the error flag is
asserted after the current byte. An interrupt is generated if the interrupt enable flag is set.
For framing error, overrun error and noise flag which are asserted with RXNE in single byte
reception, there is a separate error flag interrupt enable bit (EIE bit in the USARTx_CR3
register), which, if set, enables an interrupt after the current byte if any of these errors occur.
36.5.16 RS232 hardware flow control and RS485 driver enable
using USART
It is possible to control the serial data flow between 2 devices by using the CTS input and
the RTS output. The Figure 404 shows how to connect 2 devices in this mode:
Figure 404. Hardware flow control between 2 USARTs
7;OLQH
)UDPH
)
)
6HWE\KDUGZDUH
FOHDUHGE\'0$UHDG
)
DLE
)UDPH
)UDPH
5;1(IODJ
86$57B7'5
'0$UHTXHVW
'0$UHDGV
86$57B7'5
'0$7&,)IODJ
WUDQVIHUFRPSOHWH
6RIWZDUHFRQILJXUHVWKH
'0$WRUHFHLYHGDWD
EORFNVDQGHQDEOHV
WKH86$57
'0$UHDGV)
IURP86$57B7'5
7KH'0$WUDQVIHU
LVFRPSOHWH
7&,) LQ
'0$B,65
6HWE\KDUGZDUH
&OHDUHG
E\
VRIWZDUH
'0$UHDGV)
IURP86$57B7'5
'0$UHDGV)
IURP86$57B7'5
06Y9
7;FLUFXLW
86$57
7;
5;FLUFXLW
5;FLUFXLW
86$57
7;FLUFXLW
7;
&76
&76576
5;
576
5;