DocID024597 Rev 3 437/1693
RM0351 Analog-to-digital converters (ADC)
540
In differential input mode, the analog voltage to be converted for channel “i” is the difference
between the external voltage ADC_INi (positive input) and ADC_INi+1 (negative input).
When ADC is configured as differential mode, both input should be biased at (VREF+) / 2
voltage.
The input signal are supposed to be differential (common mode voltage should be fixed).
For a complete description of how the input channels are connected for each ADC, refer to
Figure 60: ADC1 connectivity to Figure 62: ADC3 connectivity.
Caution: When configuring the channel “i” in differential input mode, its negative input voltage is
connected to ADC_INi+1. As a consequence, channel “i+1” is no longer usable in single-
ended mode or in differential mode and must never be configured to be converted. Some
channels are shared between ADC1/ADC2/ADC3: this can make the channel on the other
ADC unusable. Only exception is interleaved mode for ADC master and the slave.
Example: Configuring ADC1_IN5 in differential input mode will make ADC12_IN6 not
usable: in that case, the channels 6 of both ADC1 and ADC2 must never be converted.
Note: Channels 16, 17 and 18 of ADC1/ADC2/ADC3 are forced to single-ended configuration
(corresponding bits DIFSEL[i] is always zero), either because connected to a single external
analog input or connected to an internal channel. The ADC channels connected to internal
voltages must be configured in single-ended mode.
16.3.8 Calibration (ADCAL, ADCALDIF, ADCx_CALFACT)
Each ADC provides an automatic calibration procedure which drives all the calibration
sequence including the power-on/off sequence of the ADC. During the procedure, the ADC
calculates a calibration factor which is 7-bit wide and which is applied internally to the ADC
until the next ADC power-off. During the calibration procedure, the application must not use
the ADC and must wait until calibration is complete.
Calibration is preliminary to any ADC operation. It removes the offset error which may vary
from chip to chip due to process or bandgap variation.
The calibration factor to be applied for single-ended input conversions is different from the
factor to be applied for differential input conversions:
• Write ADCALDIF=0 before launching a calibration which will be applied for single-
ended input conversions.
• Write ADCALDIF=1 before launching a calibration which will be applied for differential
input conversions.
The calibration is then initiated by software by setting bit ADCAL=1. Calibration can only be
initiated when the ADC is disabled (when ADEN=0). ADCAL bit stays at 1 during all the
calibration sequence. It is then cleared by hardware as soon the calibration completes. At
this time, the associated calibration factor is stored internally in the analog ADC and also in
the bits CALFACT_S[6:0] or CALFACT_D[6:0] of ADCx_CALFACT register (depending on
single-ended or differential input calibration)
The internal analog calibration is kept if the ADC is disabled (ADEN=0). However, if the ADC
is disabled for extended periods, then it is recommended that a new calibration cycle is run
before re-enabling the ADC.
The internal analog calibration is lost each time the power of the ADC is removed (example,
when the product enters in STANDBY or VBAT mode). In this case, to avoid spending time
recalibrating the ADC, it is possible to re-write the calibration factor into the
To Next Page
Loading...
Need help?
General
