Digital filter for sigma delta modulators (DFSDM) RM0351
614/1693 DocID024597 Rev 3
SPI coded stream is synchronized after first detection of clock input signal (valid
rising/falling edge).
Note: When the transceiver is not yet synchronized, the clock absence flag is set and cannot be
cleared by CLRCKABF[y] bit (in DFSDMx_ICR register).
Figure 150. First conversion for Manchester coding (Manchester synchronization)
External serial clock frequency measurement
The measuring of a channel serial clock input frequency provides a real data rate from an
external modulator, which is important for application purposes.
An external serial clock input frequency can be measured by a timer counting DFSDM
clocks (f
DFSDMCLK
) during one conversion duration. The counting starts at the first input data
clock after a conversion trigger (regular or injected) and finishes by last input data clock
before conversion ends (end of conversion flag is set). Each conversion duration (time
between first serial sample and last serial sample) is updated in counter CNVCNT[27:0] in
register DFSDMx_CNVTIMR when the conversion finishes (JEOCF=1 or REOCF=1). The
user can then compute the data rate according to the digital filter settings (FORD, FOSR,
IOSR, FAST). The external serial frequency measurement is stopped only if the filter is
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