DocID024597 Rev 3 615/1693
RM0351 Digital filter for sigma delta modulators (DFSDM)
657
bypassed (FOSR=0, only integrator is active, CNVCNT[27:0]=0 in DFSDMx_CNVTIMR
register).
In case of parallel data input (Section 21.3.6: Parallel data inputs) the measured frequency
is the average input data rate during one conversion.
Note: When conversion is interrupted (e.g. by disabling/enabling the selected channel) the
interruption time is also counted in CNVCNT[27:0]. Therefore it is recommended to not
interrupt the conversion for correct conversion duration result.
Conversion times:
injected conversion or regular conversion with FAST = 0 (or first conversion if
FAST=1):
for Sinc
x
filters (x=1..5):
t = CNVCNT/f
DFSDMCLK
= [F
OSR
* (I
OSR
-1 + F
ORD
) + F
ORD
] / f
DFSDM_CKIN
for FastSinc filter:
t = CNVCNT/f
DFSDMCLK
= [F
OSR
* (I
OSR
-1 + 4) + 2] / f
DFSDM_CKIN
regular conversion with FAST = 1 (except first conversion):
for Sinc
x
and FastSinc filters:
t = CNVCNT/f
DFSDMCLK
= [F
OSR
* I
OSR
] / f
DFSDM_CKIN
in case if F
OSR
= FOSR[9:0]+1 = 1 (filter bypassed, active only integrator):
t = I
OSR
/ f
DFSDM_CKIN
(... but CNVCNT=0)
where:
• f
DFSDM_CKIN
is the channel input clock frequency (on given channel
DFSDM_CKINypin) or input data rate (in case of parallel data input)
• F
OSR
is the filter oversampling ratio: F
OSR
= FOSR[9:0]+1 (see DFSDMx_FCR
register)
• I
OSR
is the integrator oversampling ratio: I
OSR
= IOSR[7:0]+1 (see DFSDMx_FCR
register)
• F
ORD
is the filter order: F
ORD
= FORD[2:0] (see DFSDMx_FCR register)
Channel offset setting
Each channel has its own offset setting (in register) which is finally subtracted from each
conversion result (injected or regular) from a given channel. The offset is stored as a 24-bit
signed value in OFFSET[23:0] field in DFSDM_CHCFGyR2 register.
Data right bit shift
To have the result aligned to a 24-bit value, each channel defines a number of right bit shifts
which will be applied on each conversion result (injected or regular) from a given channel.
The data bit shift number is stored in DTRBS[4:0] bits in DFSDM_CHCFGyR2 register.
The right bit-shift is rounding the result to nearest integer value. The sign of shifted result is
maintained, in order to have valid 24-bit signed format of result data.
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