DocID024597 Rev 3 729/1693
RM0351 Advanced encryption standard hardware accelerator (AES)
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To suspend mode CMAC during header phase, the user must respect the following steps:
• Before interrupting the current message:
a) Make sure that CCF flag in AES_SR is set to 1.
b) Clear CCF flag in AES_SR register by setting CCFC bit to 1 in AES_CR.
c) Save AES initialization vector registers AES_IVx and AES_SUSPxR registers in
the memory (AES_IVx registers are modified during header phase)
d) Disable AES processor by setting EN in AES_CR to 0.
e) Save the current AES configuration values in the memory.
• To resume:
f) Make sure that AES processor is disabled by reading bit EN in AES_CR.
g) Write back AES_SUSPxR registers into their corresponding suspend registers.
h) Write back AES_IVx registers into their AES initialization vector registers
i) Re-configure AES with the initial setting values in CR register and key registers.
j) Enable the AES processor by setting EN in AES_CR register.
25.8 Data type
Data are entered in the AES processor 32 bits at a time (words), by writing them in the
AES_DINR register. AES handles 128-bit data blocks. The AES_DINR or AES_DOUTR
registers must be read or written four times to handle one 128-bit data block with the MSB
first.
The system memory organization is little-endian: whatever the data type (bit, byte, 16-bit
half-word, 32-bit word) used, the less-significant data occupies the lowest address location.
Thus, there must be a bit, byte, or half-word swapping operation to be performed on data to
be written in the AES_DINR from system memory before entering the AES processor, and
the same swapping must be performed for AES data to be read from the AES_DOUTR
register to the system memory, depending on to the kind of data to be encrypted or
decrypted.
The DATATYPE bits in the AES_CR register offer different swap modes to be applied to the
AES_DINR register before sending it to the AES processor and to be applied on the
AES_DOUTR register on the data coming out from the processor (refer to Figure 180).
Note: The swapping operation concerns only the AES_DOUTR and AES_DINR registers. The
AES_KEYRx and AES_IVRx registers are not sensitive to the swap mode selected. They
have a fixed little-endian configuration (refer to Section 25.4 and Section 25.14).
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