ST STM32L4x6 User Manual

Analog-to-digital converters (ADC) RM0351
532/1693 DocID024597 Rev 3
16.6 ADC common registers
These registers define the control and status registers common to master and slave ADCs:
16.6.1 ADC Common status register (ADCx_CSR)
Address offset: 0x00 (this offset address is relative to the master ADC base address +
0x300)
Reset value: 0x0000 0000
This register provides an image of the status bits of the different ADCs. Nevertheless it is
read-only and does not allow to clear the different status bits. Instead each status bit must
be cleared by writing 0 to it in the corresponding ADCx_SR register.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res.
JQOVF_
SLV
AWD3_
SLV
AWD2_
SLV
AWD1_
SLV
JEOS_
SLV
JEOC_
SLV
OVR_
SLV
EOS_
SLV
EOC_
SLV
EOSMP_
SLV
ADRDY_
SLV
Slave ADC
rrrrrrrrr r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res.
JQOVF_
MST
AWD3_
MST
AWD2_
MST
AWD1_
MST
JEOS_
MST
JEOC_
MST
OVR_
MST
EOS_
MST
EOC_
MST
EOSMP_
MST
ADRDY_
MST
Master ADC
rrrrrrrrr r r
Bits 31:27 Reserved, must be kept at reset value.
Bit 26 JQOVF_SLV: Injected Context Queue Overflow flag of the slave ADC
This bit is a copy of the JQOVF bit in the corresponding ADCx_ISR register.
Bit 25 AWD3_SLV: Analog watchdog 3 flag of the slave ADC
This bit is a copy of the AWD3 bit in the corresponding ADCx_ISR register.
Bit 24 AWD2_SLV: Analog watchdog 2 flag of the slave ADC
This bit is a copy of the AWD2 bit in the corresponding ADCx_ISR register.
Bit 23 AWD1_SLV: Analog watchdog 1 flag of the slave ADC
This bit is a copy of the AWD1 bit in the corresponding ADCx_ISR register.
Bit 22 JEOS_SLV: End of injected sequence flag of the slave ADC
This bit is a copy of the JEOS bit in the corresponding ADCx_ISR register.
Bit 21 JEOC_SLV: End of injected conversion flag of the slave ADC
This bit is a copy of the JEOC bit in the corresponding ADCx_ISR register.
Bit 20 OVR_SLV: Overrun flag of the slave ADC
This bit is a copy of the OVR bit in the corresponding ADCx_ISR register.
Bit 19 EOS_SLV: End of regular sequence flag of the slave ADC . This bit is a copy of the EOS bit in
the corresponding ADCx_ISR register.
Bit 18 EOC_SLV: End of regular conversion of the slave ADC
This bit is a copy of the EOC bit in the corresponding ADCx_ISR register.
Bit 17 EOSMP_SLV: End of Sampling phase flag of the slave ADC
This bit is a copy of the EOSMP2 bit in the corresponding ADCx_ISR register.

ST STM32L4x6 Specifications

General

Brand	ST
Model	STM32L4x6
Category	Microcontrollers
Language	English