DocID024597 Rev 3 237/1693
RM0351 Reset and clock control (RCC)
253
6.4.25 APB1 peripheral clocks enable in Sleep and Stop modes register 1
(RCC_APB1SMENR1)
Address: 0x78
Reset value: 0xF2FE CA3FAccess: no wait state, word, half-word and byte access
Bit 8 QSPISMEN Quad SPI memory interface clocks enable during Sleep and Stop modes
Set and cleared by software.
0: QUADSPI clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: QUADSPI clocks enabled by the clock gating
(1)
during Sleep and Stop modes
Bits 7:1 Reserved, must be kept at reset value.
Bit 0 FMCSMEN: Flexible memory controller clocks enable during Sleep and Stop modes
Set and cleared by software.
0: FMC clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: FMC clocks enabled by the clock gating
(1)
during Sleep and Stop modes
1. This register only configures the clock gating, not the clock source itself. Most of the peripherals are clocked by a single
clock (AHB or APB clock), which is always disabled in Stop mode. In this case setting the bit has no effect in Stop mode.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LPTIM1
SMEN
OPAMP
SMEN
DAC1
SMEN
PWR
SMEN
Res. Res.
CAN1
SMEN
Res.
I2C3
SMEN
I2C2
SMEN
I2C1
SMEN
UART5
SMEN
UART4
SMEN
USART3
SMEN
USART2
SMEN
Res.
rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPI3
SMEN
SPI2
SMEN
Res. Res.
WWDG
SMEN
Res.
LCD
SMEN
Res. Res. Res.
TIM7
SMEN
TIM6
SMEN
TIM5
SMEN
TIM4
SMEN
TIM3
SMEN
TIM2
SMEN
rw rw rw rw rw rw rw rw rw rw
Bit 31 LPTIM1SMEN: Low power timer 1 clocks enable during Sleep and Stop modes
Set and cleared by software.
0: LPTIM1 clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: LPTIM1 clocks enabled by the clock gating
(1)
during Sleep and Stop modes
Bit 30 OPAMPSMEN: OPAMP interface clocks enable during Sleep and Stop modes
Set and cleared by software.
0: OPAMP interface clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: OPAMP interface clocks enabled by the clock gating
(1)
during Sleep and Stop modes
Bit 29 DAC1SMEN: DAC1 interface clocks enable during Sleep and Stop modes
Set and cleared by software.
0: DAC1 interface clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: DAC1 interface clocks enabled by the clock gating
(1)
during Sleep and Stop modes
Bit 28 PWRSMEN: Power interface clocks enable during Sleep and Stop modes
Set and cleared by software.
0: Power interface clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: Power interface clocks enabled by the clock gating
(1)
during Sleep and Stop modes
Bits 27:26 Reserved, must be kept at reset value.
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