ST STM32L4x6 User Manual

Reset and clock control (RCC) RM0351
236/1693 DocID024597 Rev 3
6.4.24 AHB3 peripheral clocks enable in Sleep and Stop modes register
(RCC_AHB3SMENR)
Address offset: 0x70
Reset value: 0x00000 0101
Access: no wait state, word, half-word and byte access
Bit 4 GPIOESMEN: IO port E clocks enable during Sleep and Stop modes
Set and cleared by software.
0: IO port E clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: IO port E clocks enabled by the clock gating
(1)
during Sleep and Stop modes
Bit 3 GPIODSMEN: IO port D clocks enable during Sleep and Stop modes
Set and cleared by software.
0: IO port D clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: IO port D clocks enabled by the clock gating
(1)
during Sleep and Stop modes
Bit 2 GPIOCSMEN: IO port C clocks enable during Sleep and Stop modes
Set and cleared by software.
0: IO port C clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: IO port C clocks enabled by the clock gating
(1)
during Sleep and Stop modes
Bit 1 GPIOBSMEN: IO port B clocks enable during Sleep and Stop modes
Set and cleared by software.
0: IO port B clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: IO port B clocks enabled by the clock gating
(1)
during Sleep and Stop modes
Bit 0 GPIOASMEN: IO port A clocks enable during Sleep and Stop modes
Set and cleared by software.
0: IO port A clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: IO port A clocks enabled by the clock gating
(1)
during Sleep and Stop modes
1. This register only configures the clock gating, not the clock source itself. Most of the peripherals are clocked by a single
clock (AHB or APB clock), which is always disabled in Stop mode. In this case setting the bit has no effect in Stop mode.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109 8 76543210
Res. Res. Res. Res. Res. Res. Res.
QSPI
SMEN
Res. Res. Res. Res. Res. Res. Res.
FMC
SMEN
rw rw
Bits 31:9 Reserved, must be kept at reset value.

ST STM32L4x6 Specifications

General

Brand	ST
Model	STM32L4x6
Category	Microcontrollers
Language	English