DocID024597 Rev 3 235/1693
RM0351 Reset and clock control (RCC)
253
1514131211109876543210
Res. Res.
ADC
SMEN
OTGFS
SMEN
Res. Res.
SRAM2
SMEN
Res.
GPIOH
SMEN
GPIOG
SMEN
GPIOF
SMEN
GPIOE
SMEN
GPIOD
SMEN
GPIOC
SMEN
GPIOB
SMEN
GPIOA
SMEN
rw rw rw rw rw rw rw rw rw rw rw
Bits 31:19 Reserved, must be kept at reset value.
Bit 18 RNGSMEN: Random Number Generator clocks enable during Sleep and Stop modes
Set and cleared by software.
0: Random Number Generator clocks disabled by the clock gating
(1)
during Sleep and Stop
modes
1: Random Number Generator clocks enabled by the clock gating
(1)
during Sleep and Stop
modes
Bit 17 Reserved, must be kept at reset value.
Bit 16 AESSMEN: AES accelerator clocks enable during Sleep and Stop modes
Set and cleared by software.
0: AES clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: AES clocks enabled by the clock gating
(1)
during Sleep and Stop modes
Bits 15:14 Reserved, must be kept at reset value.
Bit 13 ADCSMEN: ADC clocks enable during Sleep and Stop modes
Set and cleared by software.
0: ADC clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: ADC clocks enabled by the clock gating
(1)
during Sleep and Stop modes
Bit 12 OTGFSSMEN: OTG full speed clocks enable during Sleep and Stop modes
Set and cleared by software.
0: USB OTG full speed clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: USB OTG full speed clocks enabled by the clock gating
(1)
during Sleep and Stop modes
Bits 11:10 Reserved, must be kept at reset value.
Bit 9 SRAM2SMEN: SRAM2 interface clocks enable during Sleep and Stop modes
Set and cleared by software.
0: SRAM2 interface clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: SRAM2 interface clocks enabled by the clock gating
(1)
during Sleep and Stop modes
Bit 8 Reserved, must be kept at reset value.
Bit 7 GPIOHSMEN: IO port H clocks enable during Sleep and Stop modes
Set and cleared by software.
0: IO port H clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: IO port H clocks enabled by the clock gating
(1)
during Sleep and Stop modes
Bit 6 GPIOGSMEN: IO port G clocks enable during Sleep and Stop modes
Set and cleared by software.
0: IO port G clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: IO port G clocks enabled by the clock gating
(1)
during Sleep and Stop modes
Bit 5 GPIOFSMEN: IO port F clocks enable during Sleep and Stop modes
Set and cleared by software.
0: IO port F clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: IO port F clocks enabled by the clock gating
(1)
during Sleep and Stop modes
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