ST STM32L4x6

Advanced-control timers (TIM1/TIM8) RM0351
768/1693 DocID024597 Rev 3
In Center aligned mode, for odd values of RCR, the update event occurs either on the
overflow or on the underflow depending on when the RCR register was written and when
the counter was launched: if the RCR was written before launching the counter, the UEV
occurs on the overflow. If the RCR was written after launching the counter, the UEV occurs
on the underflow.
For example, for RCR = 3, the UEV is generated each 4th overflow or underflow event
depending on when the RCR was written.
Figure 208. Update rate examples depending on mode and TIMx_RCR register settings
06Y9
8(9
8(9
8(9
8(9
8(9
&RXQWHUDOLJQHGPRGH
(GJHDOLJQHGPRGH
8SFRXQWLQJ 'RZQFRXQWLQJ
E\6:E\6:E\6:
7,0[B5&5 
DQG
UHV\QFKURQL]DWLRQ
7,0[B5&5 
7,0[B5&5 
7,0[B5&5 
7,0[B5&5 
&RXQWHU
7,0[B&17
8(9
8SGDWHHYHQW3UHORDGUHJLVWHUVWUDQVIHUUHGWRDFWLYHUHJLVWHUVDQGXSGDWHLQWHUUXSWJHQHUDWHG
8SGDWH(YHQWLIWKHUHSHWLWLRQFRXQWHUXQGHUIORZRFFXUVZKHQWKHFRXQWHULVHTXDOWRWKHDXWRUHORDGYDOXH