Liquid crystal display controller (LCD) RM0351
664/1693 DocID024597 Rev 3
Figure 156. Static duty case 2
In this mode, the segment terminals are multiplexed and each of them control four pixels. A
pixel is activated only when both of its corresponding SEG and COM lines are active in the
same phase. In case of 1/4 duty, to deactivate pixel 0 connected to COM[0] the SEG[0]
needs to be inactive during the phase 0 when COM[0] is active. To activate pixel 0
connected to COM[1], the SEG[0] needs to be active during phase 1 when COM[1] is active
(see Figure 159). To activate pixels from 0 to 43 connected to COM[0], SEG[0:43] need to
be active during phase 0 when COM[0] is active. These considerations can be extended to
the other pixels.
8 to 1 Mux
When COM[0] is active the common driver block, also drives the 8 to 1 mux shown in
Figure 153 in order to select the content of first two RAM register locations. When COM[7] is
active, the output of the 8 to 1 mux is the content of the last two RAM locations.
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