DocID024597 Rev 3 181/1693
RM0351 Reset and clock control (RCC)
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1. Software reset, triggered by setting the BDRST bit in the Backup domain control
register (RCC_BDCR).
2. V
DD
or V
BAT
power on, if both supplies have previously been powered off.
A backup domain reset only affects the LSE oscillator, the RTC, the Backup registers and
the RCC Backup domain control register.
6.2 Clocks
Four different clock sources can be used to drive the system clock (SYSCLK):
• HSI16 (high speed internal)16 MHz RC oscillator clock
• MSI (multispeed internal) RC oscillator clock
• HSE oscillator clock, from 4 to 48 MHz
• PLL clock
The MSI is used as system clock source after startup from Reset, configured at 4 MHz.
The devices have the following additional clock sources:
• 32 kHz low speed internal RC (LSI RC) which drives the independent watchdog and
optionally the RTC used for Auto-wakeup from Stop and Standby modes.
• 32.768 kHz low speed external crystal (LSE crystal) which optionally drives the real-
time clock (RTCCLK).
Each clock source can be switched on or off independently when it is not used, to optimize
power consumption.
Several prescalers can be used to configure the AHB frequency, the high speed APB
(APB2) and the low speed APB (APB1) domains. The maximum frequency of the AHB, the
APB1 and the APB2 domains is 80 MHz.
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