Reset and clock control (RCC) RM0351
182/1693 DocID024597 Rev 3
All the peripheral clocks are derived from their bus clock (HCLK, PCLK1 or PCLK2) except:
• The 48 MHz clock, used for USB OTG FS, SDMMC and RNG. This clock is derived
(selected by software) from one of the three following sources:
– main PLL VCO (PLL48M1CLK)
– PLLSAI1 VCO (PLL48M2CLK)
– MSI clock.
When the MSI clock is auto-trimmed with the LSE, it can be used by the USB OTG FS
device.
• The ADCs clock which is derived (selected by software) from one of the three following
sources:
– system clock (SYSCLK)
– PLLSAI1 VCO (PLLADC1CLK)
– PLLSAI2 VCO (PLLADC2CLK).
• The U(S)ARTs clocks which are derived (selected by software) from one of the four
following sources:
– system clock (SYSCLK)
– HSI16 clock
– LSE clock
– APB1 or APB2 clock (PCLK1 or PCLK2 depending on which APB is mapped the
U(S)ART)
The wakeup from Stop mode is supported only when the clock is HSI16 or LSE.
• The I
2
Cs clocks which are derived (selected by software) from one of the three
following sources:
– system clock (SYSCLK)
– HSI16 clock
– APB1 clock (PCLK1)
The wakeup from Stop mode is supported only when the clock is HSI16.
• The SAI1 and SAI2 clocks which are derived (selected by software) from one of the
four following sources:
– an external clock mapped on SAI1_EXTCLK for SAI1 and SAI2_EXTCLK for
SAI2.
– PLLSAI1 VCO (PLLSAI1CLK)
– PLLSAI2 VCO (PLLSAI2CLK)
– main PLL VCO (PLLSAI3CLK)
• The SWPMI1 clock which is derived (selected by software) from one of the two
following sources:
– HSI16 clock
– APB1 clock (PCLK1)
The wakeup from Stop mode is supported only when the clock is HSI16.
• The low-power timers (LPTIMx) clock which are derived (selected by software) from
one of the five following sources:
– LSI clock
– LSE clock
– HSI16 clock
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