DocID024597 Rev 3 183/1693
RM0351 Reset and clock control (RCC)
253
– APB1 clock (PCLK1)
– External clock mapped on LPTIMx_IN1
The functionality in Stop mode (including wakeup) is supported only when the clock is
LSI or LSE, or in external clock mode.
• The RTC and LCD clock which is derived (selected by software) from one of the three
following sources:
– LSE clock
– LSI clock
– HSE clock divided by 32
The functionality in Stop mode (including wakeup) is supported only when the clock is
LSI or LSE.
• The IWDG clock which is always the LSI clock.
The RCC feeds the Cortex
®
System Timer (SysTick) external clock with the AHB clock
(HCLK) divided by 8. The SysTick can work either with this clock or directly with the Cortex
®
clock (HCLK), configurable in the SysTick Control and Status Register.
FCLK acts as Cortex
®
-M4 free-running clock. For more details refer to the STM32F3 and
STM32F4 Series Cortex
®
-M4 programming manual (PM0214)