Flexible static memory controller (FSMC) RM0351
362/1693 DocID024597 Rev 3
Note: The FMC_BWTRx register is valid only if the extended mode is set (mode B), otherwise its
content is don’t care.
Mode C - NOR Flash - OE toggling
Figure 38. ModeC read access waveforms
Table 63. FMC_BWTRx bit fields
Bit number Bit name Value to set
31-30 Reserved 0x0
29-28 ACCMOD 0x1 if extended mode is set
27-24 DATLAT Don’t care
23-20 CLKDIV Don’t care
19-16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK)
15-8 DATAST
Duration of the access second phase (DATAST HCLK cycles) for
write accesses.
7-4 ADDHLD Don’t care
3-0 ADDSET
Duration of the access first phase (ADDSET HCLK cycles) for write
accesses. Minimum value for ADDSET is 0.
!;=
./%
!$$3%4 $!4!34
-EMORYTRANSACTION
.%X
$;=
(#,+CYCLES (#,+CYCLES
.7%
.!$6
DATADRIVEN
BYMEMORY
-36
(IGH
To Next Page
Loading...
