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RM0351 Advanced encryption standard hardware accelerator (AES)
751
25 Advanced encryption standard hardware accelerator
(AES)
25.1 Introduction
The AES hardware accelerator can be used to both encipher and decipher data using AES
algorithm. It is a fully compliant implementation of the following standard:
• The advanced encryption standard (AES) as defined by Federal Information
Processing Standards Publication (FIPS PUB 197, 2001 November 26)
The accelerator encrypts and decrypts 128-bit blocks using either 128-bit or 256-bit key
length. It can also perform key derivation. The encryption or decryption key is stored in an
internal register in order to minimize write operations by the CPU or DMA when processing
several data blocks using the same key.
By default, electronic codebook mode (ECB) is selected. Cipher block chaining (CBC),
counter (CTR) mode, Galois counter (GCM) mode, Galois message authentication code
(GMAC) or cipher message authentication code mode (CMAC) chaining algorithms are also
supported by the hardware.
The AES supports DMA transfer for incoming and for outcoming data (2 DMA channels
required).
25.2 AES main features
• Encryption/decryption using AES Rijndael Block Cipher algorithm
• NIST FIPS 197 compliant implementation of AES encryption/decryption algorithm
• 256-bit register for storing the encryption, decryption or derivation key (8x 32-bit
registers)
• Electronic codebook (ECB), cipher block chaining (CBC), counter mode (CTR), Galois
counter mode (GCM), Galois message authentication code mode (GMAC) and cipher
message authentication code mode (CMAC) supported
• Key scheduler
• Key derivation for decryption
• 128-bit data block processing
• 128-bit, 256-bit key length
• 1x32-bit INPUT buffer and 1x32-bit OUTPUT buffer
• Register access supporting 32-bit data width only
• One register used as a 128-bit initialization vector when AES is configured in CBC
mode or used as a 32-bit counter initialization when CTR, GCM or CMAC mode is
selected
• Automatic data flow control with support of direct memory access (DMA) using 2
channels, one for incoming data, and one for outcoming data.
• Suspend a message if another message with a higher priority needs to be processed
• Cycles to process for each mode
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